Novel Digital Signal Processing Unit Using New Digital Baseline Wander Corrector for Fast Ethernet

摘要

This paper presents a novel digital signal processing (DSP) unit including a new baseline wander (BLW) corrector to support fast Ethernet in twisted pair (TP) cable channels. The proposed DSP unit consists of a programmable gain amplifier (PGA), timing recovery loop, adaptive equalizer and the new BLW corrector. Unlike the existing BLW correctors, the proposed BLW corrector calculates the BLW error by subtracting the equalizer input from the slicer output. Moreover, the new BLW corrector implemented in the digital domain uses four symbols to remove the BLW instead of the two symbols used in previous works. In addition, the proposed adaptive equalizer uses 2−7 as the optimum step size, i.e., μ. Since μ is a multiple of 2, the equalizer eliminates the need for multipliers and, thus, has a small area and consumes less power. To verify the performance of the proposed DSP unit, floating-point and fixed-point simulations using the SPW™ tool were performed. The measured BER is less than 10−10 when the cable length is 150 m. The proposed DSP unit was modeled by Verilog-HDL and synthesized using the 0.18 μm SEC cell library. The implemented DSP unit having 128,528 gates can operate at 142.7 MHz.