Design of High Performance 8 bit Multiplier using Vedic Multiplication Algorithm with McCMOS Technique

摘要

This paper presents a high speed low power digital multiplier by taking the advantage of Vedic multiplication algorithms with a very efficient leakage control technique called McCMOS technology. We have designed a 8 bit Vedic multiplier using Multiple channel CMOS (McCMOS) technology, by using 130 nm, 90 nm, 65 nm & 45 nm node technology and presents comparative simulation results indicating the performance of the circuit. Vedic mathematics, a system of ancient Indian mathematics, which has a unique technique of solutions based on only 16 sutras (formulae), is very useful for doing tedious and cumbersome mathematical operations done at a very fast rate. The simulations have been carried out in Cadence-Spice simulator with 1 V power supply. Thorough simulations of 8 × 8 digital Vedic multiplier using McCMOS technology show that the Power Delay Product (PDP) is reduced by ～80 % compared to the conventional multiplier design. This technique will be very useful for designing low leakage high speed ALU unit.