High-performance decimal hardware arithmetic is now a high demand due to the requirement for accurate computation in fields like commercial computing and financial analysis. The performance of fully redundant decimal multi-plier is limited because the circuit for fully redundant adder is complex. A modified fully redundant adder based on overloa-ded decimal digit set (ODDS) and a new decimal reduction tree based on fully redundant ODDS adders are proposed. The signed-digit radix-10 recoding and redundant binary coded decimal ( BCD) codes are used for fast partial product genera-tion. A recoding conversion circuit is proposed to generate BCD-8421 product fast. Comparison shows that the delay and area of the proposed decimal multiplier are small.%商业计算、金融分析等领域对高精度计算的需求对硬件十进制运算提出了越来越高的要求.已有的全冗余十进制乘法器由于全冗余加法器的结构复杂,已经给其性能的提升造成了瓶颈.本文优化设计了基于超载十进制数集(Overloaded Decimal Digit Set,ODDS)的全冗余ODDS加法器以降低其复杂度,并设计了一种新的基于该加法器的十进制压缩树模块.本文在部分积产生模块采用有符号的基-10 编码和冗余的二-十进制( Binary Coded Decimal, BCD)编码快速产生十进制部分积.在最终积产生模块采用优化的编码转换电路快速产生BCD-8421乘积.实验结果显示所设计的并行全冗余十进制乘法器速度较快、面积较小.
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