Enhancing Hardware Assisted Test Insertion Capabilities on Embedded Processors using an FPGA-based Agile Test Support Co-processor

摘要

With software defects reducing profits in many fields, it is worthwhile to consider moving key defect reducing strategies from one development area into another. However, inadequate tool support has compromised attempts to transfer Agile methodology's successes from "business systems" to embedded system development. We outline the advantages of adding an Agile test support (ATS) co-processor to provide low overhead hardware-assisted test insertion capabilities into testing frameworks for test-first (Agile) and test-last hardware-software design philosophies. We propose the development of an ATS FPGA co-processor using an extension to the eXtreme Programming Inspired (XPI) embedded lifecycle. The performance of a prototype ATS co-processor is compared to the existing instruction watch (low overhead) and data watch (high overhead) debug hardware present on Analog Devices ADSP-BF5XX Blackfin processors.