Thermal Placement Optimization of Stacked Chips Based on Partheno-genetic Algorithm

摘要

In the thermal design of stacked chips, the placement of substrate has a significant effect on temperature field, thus influencing its reliability. The thermal placement optimization of stacked chips is stvidied in this paper. The goal of this work is to decrease the highest temperature and achieve an uniform thermal field distribution. In order to optimize the thermal placement, partheno-genetic algorithm is adopted. The temperature of stacked chips is the evaluation indicator which based on thermal superposition model and heat conduction equation, therefore the fitness function of thermal placement optimization is up to the indicator. In the algorithm, the selected operator of three copies competition can maintain the diversity of the population. And new genetic operators, such as gene transposition, gene translocation, gene inversion, and gene mutation, which are all carried on a chromosome, are adopted. The genetic operators not only guarantee the new generation of individuals to be viable solutions, but also improve the searching capability. According to this work, the chips placement rules which used for directing thermal design of stacked chips are summarized. For the purpose of demonstrating the effective of the obtained optimization program, ANSYS, Finite Element Analysis (FEA), is carried out to assess the thermal field distribution of the optimization placement in stacked chips. The results show that the thermal field distribution of the optimization chips placement is in well accord with the FEA results. It turns out that the chip placement optimization approach proposed in this work is effective in decreasing the highest temperature and achieving uniform thermal field distribution.