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首页> 外文期刊>Journal of Computational Electronics >Influences of grain structure on thermally induced stresses in 3D IC inter-wafer vias
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Influences of grain structure on thermally induced stresses in 3D IC inter-wafer vias

机译:晶粒结构对3D IC晶片间通孔中热应力的影响

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We discuss the development of a grain-continuum model to examine the effects of thermally induced stress in 3D IC inter-wafer vias. We demonstrate the approach using stress-driven grain boundary migration in polycrystalline copper films, assuming that migration is due to vacancy migration. The anisotropic elastic constants of single crystal Cu are used for each grain, after aligning them with each grain's orientation. Stresses are thermally induced in a series of films, including one with a dominant < 111 > texture surrounding a single < 100 > grain. Grain boundary velocities are calculated from the fluxes of vacancies to grain boundaries. The computed velocities are then used to update the level sets that represent the grain boundaries using the PLENTE software.
机译:我们讨论了晶粒连续模型的开发,以检查3D IC晶片间通孔中热应力的影响。我们假设在多晶铜膜中使用应力驱动的晶界迁移,并假设迁移是由于空位迁移造成的,我们演示了该方法。将单晶Cu的各向异性弹性常数与每个晶粒的取向对齐后,再将其用于每个晶粒。应力是在一系列薄膜中热感应产生的,其中包括在单个<100>晶粒周围具有显着的<111>织构的薄膜。晶界速度是根据空位通向晶界的通量来计算的。然后,使用PLENTE软件将计算出的速度用于更新代表晶粒边界的水平集。

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