Optimized fault tolerant designs of the reversible barrel shifters using low power MOS transistors

摘要

This paper demonstrates the reversible logic synthesis for the unidirectional, bidirectional and universal barrel shifters. The proposed shifters are constructed using only Fredkin and Feynman double gates. Initially, these two gates are designed and schematized using standard low power p-MOS 901 and n-MOS 902 models with average channel length 45 nm, delay 0.030 ns and density 1200 kgates/mm(^2). These schemas can detect faulty signal in its primary outputs. Thus, all the proposed shifters inherently tolerate single level fault. Moreover, the presented generalized algorithm for the proposed unidirectional barrel shifter has further been used to build base structures of the proposed bidirectional and universal shifters. In addition, lower bounds on the numbers of constant inputs and garbage outputs of the reversible barrel shifter have been proposed. It has been evidenced that the proposed circuits are constructed with these optimum constant inputs and garbage outputs. The simulation results prove the functional correctness of the proposed circuits. The comparative results show that the proposed designs perform much better and have significantly better scalability than the existing approaches.