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首页> 外文期刊>Journal of Circuits, Systems, and Computers >A Full-Band Timing Mismatch Calibration Technique in Time-Interleaved ADCs
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A Full-Band Timing Mismatch Calibration Technique in Time-Interleaved ADCs

机译:时间交错ADC中的全频带时序失配校准技术

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摘要

This paper proposes a full-band calibration scheme of timing mismatch for Time-Interleaved Analog-to-Digital Converters (TI-ADC) based on Automatic Identification (AI) detection scheme. Besides estimating the value of timing mismatch, AI detection scheme also judges the odd-even property of the Nyquist zone (NZ) which the input signal belongs to and thus adaptively adjusts the calibration polarity for full-band application. On the other hand, Successive-Approximation-Register (SAR) correction technique is employed to speed up the convergence process of calibration with low cost. The efficiency of the proposed calibration scheme is verified by MATLAB simulation and implementation on PCB. Both results show that with an input signal whose bandwidth is within any NZ, the proposed calibration methodology is effective. Compared with the traditional calibration schemes, the proposed calibration method achieves fast convergence speed with 6 x 10(3) samples and costs less hardware with 2.1 k gate counts.
机译:本文提出了一种基于自动识别(AI)检测方案的时间交错式模数转换器(TI-ADC)时序失配的全频带校准方案。除了估计时序失配的值外,AI检测方案还可以判断输入信号所属的奈奎斯特区(NZ)的奇偶特性,从而自适应地调整校准极性以用于全频带应用。另一方面,采用逐次逼近寄存器(SAR)校正技术以低成本加快了校正的收敛过程。通过MATLAB仿真和在PCB上的实现,验证了所提出的校准方案的效率。两种结果都表明,对于带宽在任何NZ内的输入信号,所提出的校准方法是有效的。与传统的校准方案相比,所提出的校准方法以6 x 10(3)个样本实现了快速的收敛速度,并以2.1 k的门数减少了硬件成本。

著录项

  • 来源
    《Journal of Circuits, Systems, and Computers》 |2019年第6期|1950092.1-1950092.14|共14页
  • 作者单位

    Univ Elect Sci & Technol China, State Key Lab Elect Thin Films & Integrated Devic, Room 1003,Bldg 211,4,Sect 2,North Jianshe Rd, Chengdu 610054, Sichuan, Peoples R China;

    Univ Elect Sci & Technol China, State Key Lab Elect Thin Films & Integrated Devic, Room 1003,Bldg 211,4,Sect 2,North Jianshe Rd, Chengdu 610054, Sichuan, Peoples R China;

    Univ Elect Sci & Technol China, State Key Lab Elect Thin Films & Integrated Devic, Room 1003,Bldg 211,4,Sect 2,North Jianshe Rd, Chengdu 610054, Sichuan, Peoples R China;

    Univ Elect Sci & Technol China, State Key Lab Elect Thin Films & Integrated Devic, Room 1003,Bldg 211,4,Sect 2,North Jianshe Rd, Chengdu 610054, Sichuan, Peoples R China;

    Univ Elect Sci & Technol China, State Key Lab Elect Thin Films & Integrated Devic, Room 1003,Bldg 211,4,Sect 2,North Jianshe Rd, Chengdu 610054, Sichuan, Peoples R China;

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  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Timing mismatch; full-band calibration; time-interleaved; analog-to-digital converters;

    机译:时序不匹配;全带校准;时间交织;模数转换器;

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