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N-Path Interleaving Analog-to-Digital Converter (ADC) with Offset gain and Timing Mismatch Calibration
N-Path Interleaving Analog-to-Digital Converter (ADC) with Offset gain and Timing Mismatch Calibration
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机译:具有失调增益和时序失配校准的N路径交错模数转换器(ADC)
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摘要
A system and method are provided for calibrating timing mismatch in an n-path time interleaved analog-to-digital converter (ADC). The method digitizes an analog signal with an n-path interleaved ADC, creating an interleaved ADC signal. In a first process, the phase of the interleaved ADC signal is rotated by 90 degrees, creating a rotated signal. This rotation may be accomplished using a finite impulse response (FIR) filter with taps at {0.5, 0, −0.5}, enabled as a derivative filter, or as a Hilbert transformation. In a parallel second process, the interleaved ADC signal is delayed, creating a delayed signal. The rotated signal is multiplied by the delayed signal to create a timing error signal. Using the timing error signal, timing errors are accumulated for the ADC signal paths, and corrections are applied that minimize timing errors in each of the n ADC signal paths.
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