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首页> 外文期刊>Journal of Applied Physics >Architecture of source-drain cavity of a p-channel field effect transistor for embedding with epitaxial SiGe for enhanced performance
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Architecture of source-drain cavity of a p-channel field effect transistor for embedding with epitaxial SiGe for enhanced performance

机译:嵌入外延SiGe的p沟道场效应晶体管的源漏腔结构,可增强性能

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摘要

Increase in power consumption in field effect transistors has been curtailed in recent years by introduction of mechanical stress to achieve device speed gain over and above the traditional speed vs. power tradeoffs achieved only by scaling gate lengths. Increasingly, the source-drain region of p-channel field effect transistors are etched and epitaxial SiGe re-grown in the cavity to enhance hole mobility. However, the addition of stress as a method to improve performance would add to the process variability beyond the traditional source of lithography, now related to structure and dimension of the cavity and composition of SiGe. In this paper, compressive stress induced in the channel was directly measured using synchrotron x-ray diffraction. The samples were a set of gratings designed to map the transistor performance with varying design space. The x-ray beam was systematically stepped across the gratings at an interval of 200 nm and diffraction data collected to assess the extent of stress field. Diffraction space maps were created around the symmetric (004) and asymmetric (115) planes. Strain was deduced from Si peak shift and stress calculated from the Si elastic constants. Diffraction space maps around the asymmetric plane were used to deduce the mechanism and subsequent relaxation of strain. Diffraction data collected with x-ray beam placement close to the Si-SiGe vertical interface provided information from lateral SiGe epitaxy on the (110) plane. The presence of strained SiGe peak exhibiting tilt as well as "relaxed" SiGe peak surrounded by diffuse scattering due to dislocations were observed. The use of non-selective etch process resulted in cavity formation with multiple crystallographic planes. The subsequent relaxation mechanism that was dependent on the formation of misfit dislocations was perturbed, possibly due to pinning of the dislocations at the intersection of two crystallographic planes and served as the source of variability. Measured stress variation from 90 to 220 MPa was seen that resulted in estimated drive current enhancement variability from 5% to 15%. The maximum strain was seen where the SiGe film saw no relaxation and the energy formed due to hetero-epitaxy was transferred elastically as channel stress. The elastic relaxation was also accompanied by formation of tilted boundary. Based on these findings, the design of an ideal cavity that would maximize strain and minimize variability with layout was proposed.
机译:近年来,通过引入机械应力来实现器件速度增益超过传统速度与功率折衷(仅通过缩放栅极长度来实现)的问题,从而减少了场效应晶体管功耗的增加。越来越多地蚀刻p沟道场效应晶体管的源极-漏极区,并在空腔中重新生长外延SiGe,以增强空穴迁移率。但是,增加应力作为提高性能的一种方法将增加工艺的可变性,而不仅仅是传统的光刻技术,而光刻技术现在与腔的结构和尺寸以及SiGe的成分有关。在本文中,使用同步加速器X射线衍射直接测量通道中引起的压应力。样本是一组光栅,旨在在变化的设计空间下绘制晶体管性能。 X射线束以200 nm的间隔系统地跨过光栅,并收集衍射数据以评估应力场的程度。在对称(004)和非对称(115)平面周围创建了衍射空间图。由Si峰位移和由Si弹性常数计算出的应力推导出应变。使用非对称平面周围的衍射空间图来推导其机理和随后的应变松弛。在靠近Si-SiGe垂直界面的X射线束放置下收集的衍射数据提供了来自(110)平面上横向SiGe外延的信息。观察到存在呈现倾斜的应变SiGe峰以及由于位错而被扩散散射包围的“松弛” SiGe峰。非选择性蚀刻工艺的使用导致形成具有多个晶体学平面的腔。依赖于失配位错形成的后续弛豫机制可能受到干扰,这可能是由于位错钉扎在两个晶体学平面的相交处,并成为变异性的来源。可以看到从90到220 MPa的测量应力变化,导致估计的驱动电流增强变化从5%到15%。看到最大应变时,SiGe薄膜没有松弛,由于异质外延形成的能量作为沟道应力弹性转移。弹性松弛还伴随着倾斜边界的形成。基于这些发现,提出了一种理想的腔体设计,该腔体将最大程度地提高应变并减小布局的可变性。

著录项

  • 来源
    《Journal of Applied Physics》 |2011年第6期|p.064301.1-064301.5|共5页
  • 作者

    A. Parikh; Z. Cai;

  • 作者单位

    Technology and Manufacturing Group, Texas Instruments, 13121 TI Boulevard, Dallas, Texas 75243, USA;

    Advanced Photon Source, Argonne National Labs, Argonne, Illinois 60439, USA;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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