The reduction of keep-out zone (～10x) by the optimized novel trench structures near the through silicon vias for the application in 3-dimensional integrated circuits

摘要

The trench structure is designed and used to release the process induced stress, resulted from the different material thermal expansion coefficients, in the three-dimensional integral circuits (3-DICs). The stress in the designed trench structure is measured by the atomic force microscope-Raman technique experimentally and simulated by the full process simulation model. With the help of this simulation model, the optimized trench structure near the copper-filled through silicon via (TSV) is designed and reported. The experimental data demonstrate that the compressive stress near the TSV can be reduced from 600 MPa to 150 MPa, and the corresponding keep-out zone can also be decreased ～4 times with the designed trench structure having the depth of 10μm and the spacing distance of 8 μm to the TSV. This work provides one potential solution to release the process induced stress for the real application of 3-DICs.