Effect of increasing gate capacitance on the performance of a p-MoS_2/HfS_2 van der Waals heterostructure tunneling field-effect transistor

摘要

We propose a p-MoS2/HfS2 van der Waals (vdW) heterostructure tunneling field-effect transistor (TFET) with a type-II band alignment for future power-efficient electronics. The differences in temperature dependence between p-MoS2/HfS2 TFET and HfS2 metal-oxide-semiconductor field-effect transistor showed that the turn-on current of p-MoS2/HfS2 TFET originated from band-to-band tunneling. To suppress the impact of interface traps, reduce the subthreshold swing (SS), and increase the gate capacitance, the 25 nm Al2O3 gate dielectric was replaced with a 15 nm HfO2 layer. Additionally, a buried Ni back-gate structure was introduced to reduce the area of overlap between the gate, contact electrodes, and gate leakage along with the scaling of equivalent oxide thickness. Subsequently, enlargement of gate capacitance by three times led to the reduction of SS from 700 to 300 mV dec(-1), which verified that increasing the gate capacitance suppressed the impact of interface traps and improved gate controllability in the vdW heterostructure TFET. (C) 2019 The Japan Society of Applied Physics