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A New Two-Dimensional Analytical Model for Nanoscale Symmetrical Tri-Material Gate Stack Double Gate Metal-Oxide-Semiconductor Field Effect Transistors

机译:纳米级对称三材料栅叠层双栅金属氧化物半导体场效应晶体管的二维分析模型

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摘要

Based on the resultant solution of two-dimensional (2D) Poisson's equation in silicon region, a new, compact and analytical model for nanoscale fully depleted, symmetrical tri-material gate stack double-gate (STMGSDG) metal-oxide-semiconductor field-effect transistor (MOSFET) has been developed. The STMGSDG MOSFET exhibits significantly reduced short-channel effects (SCEs) when compared with the symmetrical single-material gate stack double-gate (SSMGSDG) MOSFET. It is found that the threshold voltage roll-off for the fully depleted STMGSDG MOSFET can be effectively reduced by using both thin Si film and thin gate oxide. Besides, the high ratio of large work function of metal gate 1 (L_1) to the total gate can efficiently suppress the drain-induced barrier lowering (DIBL) and maintain the low threshold voltage degradation. This study not only presents a precise 2D analytical model of the surface potential and threshold voltage, but also discusses the electric field distribution in the channel region, subthreshold swing and subthreshold current for the STMGSDG MOSFET. The new model is verified to be in a good agreement with numerical simulation results over a wide range of the device parameters.
机译:基于硅区域中二维(2D)泊松方程的所得解决方案,建立了一种新的,紧凑的解析模型,用于纳米级完全耗尽的对称三材料栅堆叠双栅(STMGSDG)金属氧化物半导体场效应已经开发出晶体管(MOSFET)。与对称单材料栅极堆叠双栅极(SSMGSDG)MOSFET相比,STMGSDG MOSFET显着降低了短沟道效应(SCE)。发现通过同时使用薄硅膜和薄栅极氧化物,可以有效地减少完全耗尽的STMGSDG MOSFET的阈值电压下降。此外,金属栅极1的大功函(L_1)与总栅极的高比率可以有效地抑制漏极引起的势垒降低(DIBL),并保持较低的阈值电压降级。这项研究不仅提供了表面电势和阈值电压的精确二维分析模型,而且还讨论了STMGSDG MOSFET沟道区域中的电场分布,亚阈值摆幅和亚阈值电流。经过验证,新模型与各种器件参数上的数值仿真结果均具有良好的一致性。

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  • 来源
    《Japanese journal of applied physics》 |2009年第10期|104503.1-104503.7|共7页
  • 作者单位

    Department of Electro-Optical Engineering, Southern Taiwan University, Tainan 710, Taiwan;

    Department of Electronic Engineering, Southern Taiwan University, Tainan 710, Taiwan;

    Department of Electronic Engineering, Southern Taiwan University, Tainan 710, Taiwan;

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