Improved Device Performance of GaN/AIGaN High-Electron-Mobility Transistor Using PdO Gate Interlayer

摘要

We demonstrate significant improvements of GaN/AIGaN high-electron-mobility transistors (HEMTs) by employing a PdO gate interlayer, which exhibit device performance superior to that of Pd Schottky gate HEMTs. The PdO gate interlayer effectively reduces the gate leakage current by four orders of magnitude, and it also increases the I_(on)/I_(off) ratio to four orders of magnitude. The improved AIGaN/GaN/PdO HEMT shows a nearly ideal subthreshold slope of 66 Mv/dec. The flicker noise characteristic is also observed to be lower in PdO-gate HEMTs than in Pd-Gate HEMTs. The high-work-function PdO layer and associated barrier height enhancement are the origins of the improved device performance.