Improvement of switching uniformity in Cu/SiO_2/Pt resistive memory achieved by voltage prestress

摘要

A Cu/SiO_2/Pt structure was fabricated to investigate its resistive switching characteristics. The application of DC voltages with different polarities allowed for the reversible manipulation of the structure's resistance. This resistive switching phenomenon is the result of the formation and rupture of Cu conducting filaments near the Cu/SiO_2 interface. However, significant switching dispersion occurred during Successive switching cycles, which resulted in operational difficulties and switching failure. In this study, a voltage prestress was applied to the structure in an attempt to minimize the switching dispersion. A statistical technique was used to analyze the status of formation/rupture sites, and a schematic model is proposed to explain the reason for the dispersion improvement. It is suggested that the voltage prestress builds nonconnected filaments and reduces the number of sites of filament formation/rupture. This reduction in the number of sites leads to reduced switching dispersion.