A Timing Model for CMOS Logic Gates Driving a Capacitive-resistive Load

摘要

We present a gate delay model of CMOS logic gates driving a CRCπ load for deep sub- micron technology. we extract some parameters featuring DC- and AC-characteristic of each gate beforehand. These parameters can be used for the calculation of gate delay under var- ious operating conditions including different supply voltages. The average error is 3/100 and maximum error is les8 than 11/100 in our experiments. Our method calcu1ate the gate delay about 1000 times faster than circuit simulator.