ADL-Based Specification of Implementation Styles for Functional Simulators

摘要

Functional simulators find widespread use as subsystems within micro-architectural simulators. The speed of a functional simulator is strongly influenced by its implementation style, e.g. interpreted versus binary-translated simulation. Speed is also strongly influenced by the level of detail of the interface the functional simulator presents to the rest of the timing simulator. This level of detail may change during design space exploration, requiring corresponding changes to the interface and the simulator. However, for many implementation styles, changing the interface is difficult. As a result, architects may choose either implementation styles which are more malleable or interfaces with more detail than is necessary. In either case, simulation speed is traded for simulator design time. Such a tradeoff has become particularly unfortunate as multicore processor designs proliferate and multi-threaded benchmarks must be simulated. We show that this tradeoff is unnecessary if an orthogonal-specification design principle is practiced: specify how a simulator is to be implemented separately from what it is implementing and then synthesize a simulator from the combined specifications. We show that the use of an architectural description language with constructs for implementation style specification makes it possible to synthesize interfaces with different implementation styles with reasonable effort.