Six-Side Molded Panel-Level Chip-Scale Package with Multiple Diced Wafers

摘要

In this study, the design, materials, process, assembly,and reliability of a six-side molded panel-level chip-scale package(PLCSP) are presented. Emphasis is placed on the fabrication ofthe redistribution layers (RDLs) of the PLCSP on a large temporarypanel with multiple device wafers. Because all the printedcircuited board (PCB) panels are in rectangular shape, some of thedevice wafers are diced into two or more pieces so the panel is fullyutilized. Thus, it is very high throughput. Because all the processes/equipment are PCB processes/equipment (not semiconductorprocess/equipment), it is a very low-cost process. After the fabricationof RDLs, the wafers from the PCB panel were debonded. It isfollowed by solder ball mounting and fabricating the six-sidemolded PLCSP from the original device wafers with RDLs. Thedrop test and the results including failure analysis of the PLCSPare presented. Thermal cycling of the six-side molded PLCSP PCBassembly is performed by a nonlinear temperature- and timedependentfinite-element simulation.