Current-mode analogue interface for high-speed low-current differential signalling

摘要

In this work, we propose high-speed low-current differential signalling (LCDS) over an electrical chip-to-chip interconnect by using a common-gate transimpe-dance amplifier followed by a common-source TIA stage. LCDS uses a current-mode receiver compared to a conventional voltage-mode receiver used in most of the signalling technologies such as low-voltage differential signalling, voltage-mode signalling and current-mode logic. The minimum detectable signal level possible with a current-mode receiver for the targeted bit-error rate (BER) makes LCDS an attractive choice. Also the input impedance of the LCDS receiver can be made equal to 100 Ω differential for matching the characteristic impedance of electrical chip-to-chip interconnect. The complete design, analysis and noise characterisation of the TIA front-end is presented. The CGCSTIA is implemented in 1.8 V, 0.18 μm digital CMOS technology. The input-referred noise current and 3-dB bandwidth of the receiver are 1.57μA and 5.75 GHz, respectively. For the targeted BER of 10~(-12), a data transfer rate of 6 Gb/s is achieved, while transmitting the data over a FR4 PCB trace of length 20 cm. The power dissipated in the current-mode receiver is 3.6 mW.