Retiming is a powerful technique for delay and area optimization that operates by relocating the flip-flops in a circuit. This movement of flip-flops in control logic changes the state enconding of finite state machines, requiring the preservation of initial (reset) states. Unfortunately, traditional retiming algorithms pay no regard to maintaining the initial state. While some work has been carried out on finding a retiming of a circuit with equivalent initial states, it has concentrated on achieving a specified clock period without regard to the number of flip-flops. However, if the number of flip-flops is not explcitly minimized the retimed circuit may have a very large number of flip-flops. This work targests the problem of minimizing hue number of flip-flops in control logic subject to a specifie clock period and with a guarantee of an equivalent initial state.
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