Sequential Logic Optimization by Sequential Redundancy Addition and Removal improved with Retiming

摘要

In this paper an improved optimization method for sequential synchronous circuits is introduced. The improved method uses the current main approaches "Retiming and Resynthesis" and "Redundancy Addition and Removal". The goal of the new optimization method is to combine these two techniques to get the best of each one, while overcoming the limitations of these methods that have been theoretically proven by several authors. The algorithm proposed in this paper is efficient and delivers interesting improved optimization results for the particular case of area optimization.