Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay

摘要

The use of delayed coefficient adaptaion in he least mean square (LMS) algorithm has enabled the design of pipelined architectures for real-time transversal adaptive filtering. However, the convergence speed of this delayed LMS (DLMS) algorithm, when compared with that of the standard LMS algorithm, is degraded and worsens with increase in the adaptation delay. Existing pipelined DLMS architectures have alrge adaptation delay and hence degraded convergence speed. We in this paper, firs present a pipelined DLMS architecture with minimal adaptation delay for any given sampling rate. The architecture is synthesized by using a number of function preserving transformations on the signal flow graph representation of the DLMS algorithm. With the use of carry-save arithmetic, the pipelined architecture can support high sampling rates, limited only by trhe delay of a full adder and a 2-to-1 multiplexer. In the second part of this paper, we extend the synthesis methodology described in the firs part, to synthesize pipelined DLMS architectures whose power dissipation meets a specified budget. This low-power architecutre explits the parallelism in the DLMS algorithm to meet the requried computational throughput. The architecture exhibits a novel tradeoff between algorithmic performance (convergence speed) and power dissipation.