Verification and revision of the power-down mode for hierarchical analog circuits

摘要

Specialized power-down circuitry can switch off an analog circuit when not required for system operation. When interconnecting sub-circuits with power-down functionality, new design errors, i.e. short-circuit paths, floating nodes and asymmetrical voltages at matched structures, may emerge in the power-down mode of the resulting hierarchical circuit. This paper presents a new method for the verification of the power-down mode of hierarchical analog circuits. In contrast to flat verification approaches, intermediate results are reused during computation. The obtained verification results can be used to revise and correct detected errors. Experimental results for a high input impedance differential amplifier are given.