Power-gating Schemes of MOS Current Mode Logic Circuits for Power-down Applications

摘要

With the increasing demand for battery-operated mobile platforms, energy-efficient designs have become more and more important for nanometer CMOS circuits. Compared Conventional Cmos Voltage-mode Logic (CMOSVML), MOS Current-Mode Logic (MCML) can operate at a high frequency. However, the MCML circuits have larger static power consumptions than CMOSVML ones due to their constant operation currents. In this paper, various power-gating schemes for MCML circuits are addressed to reduce their static power dissipations in sleep mode. The power-gating switches of the four power-gating schemes are realized by the PMOS transistors for linear load resistors of MCML circuits, the additional high-threshold PMOS transistor, the bias NMOS transistor for MCML circuits and the additional high-threshold NMOS transistor, respectively. The structure and operation of the proposed power-gating schemes are presented. In order to verify the correctness of the proposed power-gating schemes, a mode-10 counter based on MCML circuits are realized. All the circuits are simulated with HSPICE at SMIC 130 nm CMOS technology. The simulation results show that the power dissipations of the MCML circuits can be greatly reduced by shutting down their idle logic blocks. The proposed power-gating MCML circuits can be used for low-power high-speed applications.