Partial Scan Design Methods Based on n-Fold Line-Up Structures and the State Justification of Pure Load/Hold Flip-Flops

摘要

We will present a partial scan design method based on n-fold line-up structures in order to achieve high fault efficiency and reduce test pattern generation time for practical LSIs. We will also present a partial scan design method based on the state justification of pure load/hold FFs in order to achieve high fault efficiency and reduce the number of scan FFs for prac- tical LSIs with lots of load/hold FFs, Experimental results for practical LSIs show that our presented methods can achieve high fault efficiency (more than 99/100) and reduce the number of scan FFs for the LSI with lots of load/hold FFS.