A New Clock Routing Algorithm Using Link-Edge Insertion for High Performance IC Design

摘要

As the clock shew is one of the major con- straints for high speed synchronous Ics, it must be minimized in order to obtain high performance. But clock skew minimiza- tion may increase the total wire length; therefore, clock routing is performed within the given skew bound. Clock routing un- der the specified skew bound can decrease the total wire length. A new efficient algorithm for bounded clock skew routing using Link-edge insertion is proposed in this paper.