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LSI Design Flow for Shot Reduction of Character Projection Electron Beam Direct Writing Using Combined Cell Stencil

机译:利用组合单元模板减少字符投影电子束直接写入的压射的LSI设计流程

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摘要

We propose a shot reduction technique of character projection (CP) Electron Beam Direct Writing (EBDW) using combined cell stencil (CCS) or the advanced process technology. CP EBDW is expected both to reduce mask costs and to realize quick turn around time. One of major issue of the conventional CP EBDW, however, is a throughput of lithography. The throughput is determined by numbers of shots, which are proportional to numbers of cell instances in LSIs. The conventional shot reduction techniques focus on optimization of cell stencil extraction, without any modifications on designed LSI mask patterns. The proposed technique employs the proposed combined cell stencil, with proposed modified design flow, for further shot reduction. We demonstrate 22.4% shot reduction within 4.3% area increase for a microprocessor and 28.6% shot reduction for IWLS benchmarks compared with the conventional technique.
机译:我们提出了一种使用组合单元模板(CCS)或先进工艺技术的字符投影(CP)电子束直接书写(EBDW)的压射减少技术。预计CP EBDW既可以减少掩模成本,又可以实现快速的周转时间。然而,常规CP EBDW的主要问题之一是光刻的生产量。吞吐量由镜头数量决定,该数量与LSI中的单元实例数量成比例。传统的压丸减少技术专注于优化单元模板的提取,而无需对设计的LSI掩模图案进行任何修改。所提出的技术采用了所提出的组合单元模板以及所提出的修改后的设计流程,以进一步减少喷丸。与传统技术相比,我们证明了在微处理器增加4.3%的面积内减少22.4%的喷丸,对于IWLS基准测试减少了28.6%的喷丸。

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