A New Low-Power 13.56-MHz CMOS Ring Oscillator with Low Sensitivity of fosc to V_(DD)

摘要

A design of a low-power CMOS ring oscillator for an application to a 13.56 MHz clock generator in an implantable RFID tag is proposed. The circuit is based on a novel voltage inverter, which is an improved version of the conventional current-source loaded inverter. The proposed circuit enables low-power operation and low sensitivity of the oscillation frequency, fosc, to decay of the power supply V_(Dd). By employing a g_m-boosting subcircuit, power dissipation is decreased to 49μW at fosc = 13.56 MHz. The sensitivity of fosc to V_(DD) is reduced to -0.02 at fosc = 13.56 MHz thanks to the use of composite high-impedance current sources.