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Simulation Study of a Novel Collector-up npn InGaP/GaAs Heterojunction Bipolar Transistor with a p-Type Doping Buried Layer for Current Confinement

机译:新型集电极npn InGaP / GaAs异质结双极晶体管,具有p型掺杂埋层的电流限制仿真研究

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摘要

In this paper, we report a new collector-up npn heterojunction bipolar transistor (C-up HBT) which employs a p-type doping buried layer inserted between extrinsic emitter and subemitter for current confinement. A theoretical study is performed to verify the functionality of the p-type doping buried layer using a two-dimensional device simulator. The structural parameters of the device and bias conditions on the buried layer are investigated to understand the limitations and the potential of devices. It is found that the emitter structure should be optimized to achieve the high efficiency of current confinement and the design of overlap between base-collector junction and buried layer is effective to suppress the carrier-blocking effect. Moreover, proposed C-up HBT demonstrates the similar current-gain cutoff frequency (f_T) characteristics compared with conventional C-up HBT fabricated by ion implantations. The impact of f_T caused by the external base-emitter capacitance (C_(BE,ext)) can be relieved by further structural optimization of the emitter layer and lateral scaling of the extrinsic region. To clarify the feasibility of the proposed C-up HBTs, we also specify the fabrication process for the devices with epitaxial regrowth techniques.
机译:在本文中,我们报告了一种新的集电极-向上npn异质结双极晶体管(C-up HBT),该晶体管在外部发射极和子发射极之间插入p型掺杂掩埋层以限制电流。使用二维器件模拟器进行了理论研究,以验证p型掺杂掩埋层的功能。研究器件的结构参数和掩埋层上的偏压条件,以了解器件的局限性和潜力。发现应优化发射极结构以实现电流限制的高效率,并且基极-集电极结与掩埋层之间的重叠设计可有效抑制载流子阻挡效应。此外,与通过离子注入制造的常规C-up HBT相比,拟议的C-up HBT展示了相似的电流增益截止频率(f_T)特性。外部基极-发射极电容(C_(BE,ext))引起的f_T的影响可以通过进一步优化发射极层的结构和外部区域的横向缩放来缓解。为了阐明提议的C-up HBT的可行性,我们还指定了采用外延再生技术的器件的制造工艺。

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