首页> 外文期刊>IEICE Transactions on Electronics >Design of High-Speed High-Density Parallel Adders and Multipliers Using Regenerative Pass-Transistor Logic
【24h】

Design of High-Speed High-Density Parallel Adders and Multipliers Using Regenerative Pass-Transistor Logic

机译:再生通过晶体管逻辑设计高速高密度并行加法器和乘法器

获取原文
获取原文并翻译 | 示例

摘要

Regenerative Pass-transistor Logic (RPL), a modular dual-rail circuit technique for high speed logic design that gives reasonably low power consumption, was discussed in previous work. RPL combines advantages of both the compact size of CPL and the full voltage-swing of DPL, and gives reasonably high performance concerning both speed and power consumption. In this paper, the application and design technique of RPL on larger logic circuits and systems are reported. Parallel adders and Booth multipliers with different sizes and structures are used as examples to evaluate the functionality of the RPL gates and full adder. In addition, there is less signal skew in RPL circuits than in conventional CPL circuits when an arrangement of single-rail to dual-rail signal conversion is performed. And, RPL is found to be useful in design of high speed and high density parallel adders and multipliers.
机译:再生传输晶体管逻辑(RPL)是一种用于高速逻辑设计的模块化双轨电路技术,具有较低的功耗,在先前的工作中已进行了讨论。 RPL结合了CPL的紧凑尺寸和DPL的全电压摆幅的优点,并且在速度和功耗方面都具有相当高的性能。本文报道了RPL在大型逻辑电路和系统上的应用和设计技术。使用具有不同大小和结构的并行加法器和Booth乘法器作为示例来评估RPL门和完整加法器的功能。另外,当执行单轨到双轨信号转换的布置时,与传统的CPL电路相比,RPL电路中的信号偏斜更少。而且,发现RPL在设计高速和高密度并行加法器和乘法器时很有用。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号