Design and Simulation of Self-Aligned Vertical Island Single Electron Transistor (VI-SET) with Electrical Tunneling Barrier

摘要

Single electron transistors (SETs) are lively searched as a promising device beyond the scaling limits of CMOS (Complementary Metal Oxide Semiconductor) devices. Among the various SETs that have been reported, the vertical island (VI) SET uses a fabrication process which is compatible with CMOS and has the advantage of effectively controlling the device characteristics with its device parameters. Device simulation is performed to optimize the device parameters, and a structure that may operate the presentation of various function in the circuit and device. VI-SET device will be using the multi function circuit and qubit through the double quantum dot in the devices.