Method for forming a vertical trench transistor (self-aligned drain / channel junction for the device miniaturization in the design of the vertical pass transistor DRAM cell)

摘要

It leads to variations in the thresholds that are SOLVED] improved to provide scalability of the channel length superior to devices existing in the prior art, to produce a vertical metal oxide semiconductor field effect transistor (MOSFET). A method of forming a [MEANS FOR SOLVING PROBLEMS] vertical-type deep trench transistor is provided. Deep trench having sidewalls in the semiconductor substrate which is doped is formed. Includes on its surface in the drain region that is counter-doped, semiconductor substrate includes a channel arranged in the side wall. The drain region has a lower level and upper level. Are formed in the substrate source region is counter-doped juxtaposed side walls of the lower channel. The gate oxide layer is formed on the sidewalls of the trench juxtaposed with a gate conductor. Following the step of recessing the gate conductor to below the lower level of the drain region, at an angle θ + δ with respect to a vertical line, a step of performing a tilt ion implantation of counter dopant in the channel below the source region, a vertical line at an angle θ for, I do performing a tilt ion implantation of dopants in the channel below the source region. [Selection Figure 8