Clock frequency and latency in synchronous digital systems

摘要

The tradeoffs in the design of synchronous digital systems between clock frequency and latency in terms of the circuit characteristics of a pipelined data path are described. A design paradigm relating latency and clock frequency as a function of the level of pipelining is developed for studying the performance of a synchronous system. This perspective permits the development of design equations for constrained and unconstrained design problems which describe these performance parameters in terms of the delays of the logic, interconnect, registers, clock skew, and the number of logic states. These results provide an approach to the design of those synchronous digital systems in which latency and clock frequency are of primary importance. From the behavioral specifications for the proposed system, the designer can use these results to select the best logic architecture and the best available device technology to determine if the performance specifications can be satisfied, and, if so, what design options are available for optimization of other system attributes, such as area.