Delaying clock and data signals to force synchronous operation in digital systems that determine phase relationships between clocks with related frequencies

摘要

A method and apparatus forces synchronous operation in a system that determines a phase-based relationship between two clocks by providing selectable delays of clock and data signals. A sending IC transmits data to the receiving IC over a data bus, and provides a strobe (clock) signal to validate data at the receiving IC. The phase relationship between the strobe signal and the internal clock of receiving IC is initially unknown. Within the receiving IC, the strobe signal is used to form four clock signals that clock data into four flip flops using a round robin scheme. Each of the round robin flip flops has a valid read window, and pair of multiplexors route the outputs of the round robin flip flops to a pair of flip flops that are clocked using internal clocks of the receiving IC. A select signal in the clock domain of the receiving IC is provided to the pair of multiplexors. The select signal can have one of two possible orientations. A phase detection circuit selects the proper orientation. Asynchronous behavior can occur if the initial timing of the select signal is close to the point at which the phase detection circuit decides whether to toggle the select signal, thereby making it difficult to debug hardware bugs associated with the orientation of the select signal. The present invention solves this problem by providing a selectable delay capable of delaying data and strobe signals by either one or three validation edges of the strobe signal, or not delaying the data and strobe signal, thereby forcing a particular orientation of the select signal and possibly causing an intermittent bug to become a repeatable bug.