Method for processing respective first and second digital video data signals which are clocked by first and second clock signals having identical frequency and having a constant phase relationship with each other, and a video signal processor for processing the video data signals

摘要

A video signal processor (1) for converting standard definition and progressive scan video data signals from digital form to analogue form comprises a video signal processing circuit (7) in which the signals are converted. The respective standard and progressive video data signals are received on first and second clock signals CLOCK_—1 and CLOCK_—2, respectively, which are of identical frequency and have a constant phase relationship. An interface circuit (10) for interfacing the standard definition and progressive scan video data signals with the video signal processor (7) comprises a first register (20) into which the progressive scan signal is clocked on the second clock signal CLOCK_—2. The progressive scan signal is clocked from the first register (20) to a second register (21) by the first clock signal CLOCK_—1 and in turn from the second register (21) to a third register (22) by the first clock signal CLOCK_—1. The progressive scan signal is clocked into the second register (21) on either the rising or falling edges of the first clock signal CLOCK_—1, and the edges of the first clock signal CLOCK_—1 on which the progressive scan signal is clocked into the second register (21) is determined by the phase shift between the respective clock signals in order that the set-up time and hold time of the progressive scan signal is sufficient for clocking the signal into the second register (21). The standard definition video data signal is clocked through fourth, fifth and sixth registers (23) to (25), respectively so that the standard definition and progressive scan signals remain in time with each other both signals are clocked from the third and sixth registers (22) and (25), respectively on the rising edges of the first clock signal CLOCK_—1 into the video signal processor (7). Thus, only a single frequency multiplier circuit (17) is required in the video signal processing circuit (7) for providing clock signals for interpolating the respective standard definition and progressive scan signals.