Fixed-Point Analysis and Parameter Optimization of the Radix- src='/images/tex/20080.gif' alt='2^{k}'> Pipelined FFT Processor

摘要

The radix- algorithm plays a crucial role in the pipelined implementation of fast Fourier transform (FFT). This paper presents a fixed-point analysis and hardware evaluation of radix- FFT under the framework of the single-path delay feedback (SDF) and multi-path delay commutator (MDC) pipelined structure. The investigation is carried out with variable operating word-lengths to ensure the generality. Furthermore, the main streams to fulfill FFT coefficients weighting, namely, the approach using complex multipliers and the one adopting memoryless CORDIC units, are both considered in the analysis. Based on these derivations, a joint optimization of radix- algorithm and operating word-length is discussed to achieve a reasonable trade-off between computational accuracy and hardware expenditure. Simulations and experiments indicates that the derived SQNR is reliable to unfold the quantization effects of fixed-point radix- FFT. In addition, the proposed joint optimization strategy is capable of providing better solutions to implement the radix- FFT processor efficiently.