Comments on 'Residue arithmetic VLSI array architecture for manipulator pseudo-inverse Jacobian computation' (with reply)

摘要

The commenter indicates that in the above-mentioned paper (see ibid., vol.5, no.5, p.569-82 (1989)) the proposed pipelined array architecture for the mixed-radix conversion problem is not as efficient and suitable for VLSI implementation as claimed. The commenter identifies the shortcomings of the design and then gives an efficient systolic/wavefront array that requires fewer hardware resources. The authors reply that this is another valid design for the mixed-radix conversion problem that avoids broadcasting; however, the triangular array of buffers is still required in the design for the data-format conversion, and this problem is not addressed. Since a semisystolic design was not given, the comparison between the original design and the semisystolic design in terms of buffers is premature.