Electron trap generation in high-/spl kappa/ gate stacks by constant voltage stress

摘要

Positive bias constant voltage stress combined with charge pumping (CP) measurements were applied to study trap generation phenomena in SiO/sub 2//HfO/sub 2//TiN stacks. Using gate stacks with varying thicknesses of the interfacial SiO/sub 2/ layer (IL) or high-/spl kappa/ layer and analysis for frequency-dependent CP data developed to address trap depth profiling, the authors have determined that the defect generation in the stress voltage range of practical importance occurs primarily within the IL on as-grown "precursor" defects most likely caused by the overlaying HfO/sub 2/ layer. The generated traps can be passivated by a forming gas or nitrogen (N/sub 2/) anneal, whereas a postanneal stress reactivates these defects. The results obtained identify the IL as one of the major targets for reliability improvement of high-/spl kappa/ stacks.