Dummy Read Scheme for Lifetime Improvement of MLC NAND Flash Memories

摘要

Program/erase cycling endurance is one of the most critical reliability challenges for multi-level NAND flash memories. Deliberately designed delay between cycles is found to extend the endurance of nanoscale NAND flash memory cells. In addition, the effect of chip temperature is extensively investigated. A new dummy read operation scheme is proposed to further enhance cell reliability by effectively suppressing cycling-induced error bits in gigabit memory arrays.