Test pattern generation for circuits with tri-state modules by Z-algorithm

摘要

An algorithmic test pattern generation method named ZALG* for circuits including tri-state modules that have been extensively used in recent MOS VLSI is presented. For the circuits, special attention must be paid to bus clash and memory retention in order to avoid device destruction in testing. Since ZALG* takes complete measures against bus clash and memory retention and uses a multiple-path sensitization method, like PODEM, it is a complete algorithm in the sense that all possible combinations of input values will be tried in the worst case. ZALG* is implemented by FORTRAN, and some experimental results for circuits with two to three thousand gates are reported.