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An accurate and efficient delay time modeling for MOS logic circuits using polynomial approximation

机译:使用多项式逼近对MOS逻辑电路进行准确而有效的延迟时间建模

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A delay model for multiple delay simulation for NMOS and CMOS logic circuits is proposed. For the simple inverter the rise or fall delay time is approximated by a product of polynomials of the input waveform slope, the output loading capacitance, and the device configuration ratio, with the polynomial coefficients determined so as to best fit the SPICE simulation results for a given fabrication process. This approach can easily be extended to the case of multiple-input transitions. The simulation results show that the proposed modes can predict the delay times within 5% error and with a speedup of three orders of magnitude for several circuits tested as compared with the SPICE simulation.
机译:提出了一种用于NMOS和CMOS逻辑电路的多重延迟仿真的延迟模型。对于简单的逆变器,上升或下降延迟时间由输入波形斜率的多项式,输出负载电容和器件配置比的乘积估算,并确定多项式系数,以便最适合于SPICE仿真结果。给定的制造过程。这种方法可以轻松地扩展到多输入转换的情况。仿真结果表明,与SPICE仿真相比,对于几种测试电路,所提出的模式可以预测5%误差以内的延迟时间,并且加速三个数量级。

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