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Synthesis of arithmetic hardware using hardware metafunctions

机译:使用硬件元函数合成算术硬件

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The development of theorem-based design methods is considered. Theorem-based design uses formal logic to create provably correct implementations. Past work has focused on using formal logic and post-hoc proof for design verification. Here, the focus is on hardware synthesis functions, called hardware metafunctions, which synthesize hardware in a provably correct manner. Designs produced using the metafunctions are correct-by-construction and are formally related to their specifications by simple substitution or rewriting of terms within the correctness theorem for each metafunction. Typically, the metafunctions are parametric and, once proven correct, validate an entire class of designs. Theorem-based design is practical when the metafunctions and their proofs of correctness are machine-executable. This is accomplished using appropriate declarative languages with a strong formal basis and by developing the proofs of correctness using automatic theorem provers. The functional language SCHEME is used along with the Higher Order Logic (HOL) proof checker. An introduction to the use of higher-order logic as a design along with the verification of an adder array metafunction for an array multiplier is presented.
机译:考虑了基于定理的设计方法的发展。基于定理的设计使用形式逻辑来创建可证明正确的实现。过去的工作集中在使用形式逻辑和事后证明进行设计验证。在此,重点是称为硬件元功能的硬件综合功能,该功能以可证明的正确方式综合了硬件。使用元功能生成的设计是按构造正确的,并且通过在每个元功能的正确性定理内简单替换或重写术语而正式与其规格相关。通常,元功能是参数化的,一旦证明正确,就可以验证整个设计类别。当元功能及其正确性证明是机器可执行的时,基于定理的设计是实用的。这可以通过使用具有强大形式基础的适当声明性语言以及使用自动定理证明者开发正确性证明来实现。功能语言SCHEME与高阶逻辑(HOL)证明检查器一起使用。介绍了如何使用高阶逻辑作为设计,以及如何验证数组乘法器的加法器数组元功能。

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