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首页> 外文期刊>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems >Addendum to 'Synthesis of robust delay-fault testable circuits: Theory'
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Addendum to 'Synthesis of robust delay-fault testable circuits: Theory'

机译:“健壮的延迟故障可测试电路的合成:理论”的附录

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For original paper see ibid., vol. 11, pp. 87-101 (Jan. 1992). The robust nature of the gate delay fault tests corresponding to Theorems 7 and 8 in the original paper is clarified and described in greater detail. There are two types of robust tests for gate delay faults: a hazard-free robust test for a gate delay fault on a gate g is a robust test where only paths that pass through g are event sensitized; a general robust test for a gate delay fault on a gate g is a robust test where paths that do not pass through g can be event sensitized. The two types of robust tests are illustrated.
机译:有关原始纸张,请参见同上,第1卷。 11,第87-101页(1992年1月)。阐明并详细描述了与原论文定理7和8相对应的门延迟故障测试的鲁棒性。对于门延迟故障,有两种鲁棒性测试:对门g上的门延迟故障的无风险鲁棒性测试是仅通过g的路径对事件敏感的鲁棒性测试。对于门g上的门延迟故障的一般鲁棒性测试是一种鲁棒性测试,其中不经过g的路径可以被事件感知。说明了两种类型的鲁棒性测试。

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