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Probability distribution of signal arrival times using Bayesian networks

机译:使用贝叶斯网络的信号到达时间的概率分布

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This paper presents a new method based on Bayesian networks (BNs) for computing the exact probability distribution of the delay of a circuit. The method is based on BNs, which allows an efficient means to factor the joint probability distributions over variables in a circuit graph. The space complexity of the method presented here is O(m/sup |C|/), where m is the number of distinct values taken by each delay variable and |C| is the number of variables in the largest clique. The maximum clique size present in a BN is shown to be much smaller than the circuit size. For large circuits, where it is not practically feasible to compute the exact distribution, methods to reduce the problem size and get a lower bound on the exact distribution are presented. Comparison of the results with Monte Carlo simulations shows that we can reduce the size of the circuit by as much as 89% while maintaining the maximum difference between the predicted and simulated 3/spl sigma/ values to be less than 3%.
机译:本文提出了一种基于贝叶斯网络(BNs)的新方法,用于计算电路延迟的精确概率分布。该方法基于BN,它提供了一种有效的方法来分解电路图中变量上的联合概率分布。这里介绍的方法的空间复杂度是O(m / sup | C | /),其中m是每个延迟变量和| C |所取的不同值的数量。是最大集团中的变量数。 BN中存在的最大派系大小显示为比电路大小小得多。对于大型电路,计算精确分布实际上不可行,提出了减小问题大小并获得精确分布下限的方法。结果与蒙特卡洛模拟的比较表明,我们可以将电路尺寸减小多达89%,同时将预测值和模拟值3 / spl sigma /之间的最大差值保持在小于3%。

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