Unified and Scalable Digit-Serial Systolic Array for Multiplication and Division Over GF (2m)

摘要

This brief offers a new unified and scalable digit-serial systolic array structure to implement the unified Stein's multiplication and division algorithm. The proposed structure is flexible enough to help the designer select the required number of processing elements and manage the latency of the multiplication/division operations. Thus, the proposed design can realize the required time performance with minimum space complexity. The implementation results of the proposed design and the previously reported digit-serial competitor designs display that the proposed scalable architecture has better performance for 32-bit embedded cryptographic processors that need reasonable performance with a small footprint.