Fault modeling of physical failures in CMOS VLSI circuits

摘要

The analog complex physical fault of a gate-to-drain short in VLSI CMOS circuits is studied. A relationship between the inverse voltage of an inverter and the faulty voltage output is obtained and is then used to study the propagation of the faulty signal through successive gates. General graphical rules are developed which describe techniques for obtaining the operating point of the circuit through table look-up procedures. The technique is simple and can easily be added to known fault-simulation algorithms.