Roundoff Noise Analysis in Digital Systems for Arbitrary Sampling Rate Conversion

摘要

In this brief, the impact of finite-signal wordlengths on the performance of digital systems for arbitrary sampling rate conversion (ASRC), where input and output sampling rates are derived from independent clock generators, is investigated. For two different efficient realizations of ASRC the noise power due to both, input/output quantization and multiplication roundoff errors, is determined as a function of the signal wordlengths and system parameters, respectively. The obtained system degradation, estimated on basis of the standard model of quantization by rounding, is verified by simulation. As a result, simple design rules for the appropriate selection of the various ASRC-inherent signal wordlengths are given subject to the required system performance.