Methodology for On-Chip Adaptive Jitter Minimization in Phase-Locked Loops

摘要

This paper describes a run-time adaptive method of minimizing jitter for a phase-locked loop (PLL). The design employs digital tuning that independently adjusts each loop parameter of the PLL. The loop is fabricated in 0.25-μm CMOS and uses 2.5-V supply. The proposed method measures the output jitter on-chip and adjusts the PLL loop parameters toward minimizing the jitter by a closed-loop control system. The experimental results verify the success of the proposed method in minimizing jitter to within 5 ps of the minimum pcak-to-peak jitter.