首页> 外文期刊>IEEE transactions on circuits and systems . I , Regular papers >A Low-Power Multicarrier-CDMA Downlink Baseband Receiver for Future Cellular Communication Systems
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A Low-Power Multicarrier-CDMA Downlink Baseband Receiver for Future Cellular Communication Systems

机译:适用于未来蜂窝通信系统的低功率多载波CDMA下行链路基带接收器

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摘要

In this paper, design and implementation of a baseband receiver integrated circuit (IC) for a downlink multi-carrier code-division multiple access (MC-CDMA) system are presented. This MC-CDMA system aims to provide higher data transmission capacity than the current wide-band CDMA systems in mobile cellular communication environments. The proposed chip provides a robust tracking mechanism for synchronization errors and an accurate channel estimation strategy to overcome the challenge of outdoor fast-fading channels. Besides, low-power and low-complexity architecture design techniques are adopted to satisfy mobile receiver needs. Experimental results of the designed baseband receiver integrated circuit demonstrate its superior system performance and great reduction in power consumption. The chip was fabricated in a 0.18-mum CMOS technology with a core area of 2.6 mm times 2.6 mm. It can support up to 21.7-Mbps uncoded data rate in a 5-MHz bandwidth. When running at 5.76 MHz, its power consumption is as low as 9.9 mW from a supply voltage of 1.1 V.
机译:本文提出了一种用于下行链路多载波码分多址(MC-CDMA)系统的基带接收机集成电路(IC)的设计和实现。该MC-CDMA系统旨在在移动蜂窝通信环境中提供比当前的宽带CDMA系统更高的数据传输容量。所提出的芯片提供了一种鲁棒的同步误差跟踪机制和一种精确的信道估计策略,以克服室外快速衰落信道的挑战。此外,还采用了低功耗,低复杂度的架构设计技术来满足移动接收机的需求。设计的基带接收器集成电路的实验结果表明,它具有出色的系统性能并大大降低了功耗。该芯片采用0.18微米CMOS技术制造,核心面积为2.6毫米乘以2.6毫米。它可以在5MHz带宽中支持高达21.7-Mbps的未编码数据速率。当以5.76 MHz运行时,其功耗从1.1 V的电源电压低至9.9 mW。

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