Low-Latency High-Throughput Systolic Multipliers Over src='/images/tex/785.gif' alt='GF(2^{m})'> for NIST Recommended Pentanomials

摘要

Recently, finite field multipliers having high-throughput rate and low-latency have gained great attention in emerging cryptographic systems, but such multipliers over for National Institute Standard Technology (NIST) pentanomials are not so abundant. In this paper, we present two pairs of low-latency and high-throughput bit-parallel and digit-serial systolic multipliers based on NIST pentanomials. We propose a novel decomposition technique to realize the multiplication by several parallel arrays in a 2-dimensional (2-D) systolic structure (BP-I) with a critical-path of , where is the propagation delay of an XOR gate. The parallel arrays in 2-D systolic structure are then projected along vertical direction to obtain a digit-serial structure (DS-I) with the same critical-path. For high-throughput applications, we present another pair of bit-parallel (BP-II) and digit-serial (DS-II) structures based on a novel modular reduction technique, where the critical-path is reduced to , being the propagation delay of an AND gate. A strategy for data sharing between a pair of processing elements (PEs) of adjacent systolic arrays has been proposed to reduce area-complexity of BP-I and BP-II further. From synthesis results, it is shown that the proposed multipliers have significantly lower latency and higher throughput than the existing designs. To the best of authors' knowledge, this is the first report on low-latency systolic multipliers for finite fields where latency is independent of field-order.